A field programmable gate array (FPGA) is an integrated circuit in which the circuit configuration information can be changed by a user after it is manufactured and is now used in a variety of devices.
FIG. 1 is a configuration diagram before an update of a conventional system.
A system 101 includes a micro processing unit (MPU) 111, a memory 121, an MPU flash memory (FMEM) 131, an FPGA FMEM 141, an FPGA 151, control devices 161-i (i=1 to m), and a communication unit 171.
The MPU FMEM 131 stores a firm package 132.
The firm package 132 includes MPU firmware 133 and FPGA data 135.
The MPU firmware 133 is a program that gives instructions to perform an updating of the firm package 132, reconfiguration of the FPGA 151, etc.
The FPGA data 135 is information on circuits to be configured within the FPGA 151.
The FPGA FMEM 141 stores FPGA data 142.
The MPU 111 copies the FPGA data 135 within the MPU FMEM 131 to the FPGA FMEM 141. The FPGA data copied to the FPGA FMEM 141 is represented as the FPGA data 142. In other words, the contents of the FPGA data 135 and those of the FPGA data 142 are the same.
When the MPU 111 gives instructions to perform reconfiguration to the FPGA 151, the FPGA 151 reads the FPGA data 142 and configures circuits within the FPGA 151 based on the FPGA data 142.
When circuits are configured within the FPGA 151 based on the FPGA data 142 before an update, old circuits 181-1 to 181-n are configured. Hereinafter, the old circuits 181-1 to 181-n are represented as old circuits 1 to n, respectively.
The old circuits 1 to n are circuits that operate by normal system operation, such as control of the control device 161.
Further, within the FPGA 151, failures of elements (failed portions 1 and 2) exist in an area not used by the old circuits 1 to n.
The failed portions 1 and 2 exist in the area not used by the old circuits 1 to n, and therefore, the old circuits 1 to n operate normally.
In the case where the FPGA 151 is updated, the MPU 111 receives the new firm package 132 via the communication unit 171 and stores it in the MPU FMEM 131 and thus updates the firm package 132. Then, the MPU 111 reads the FPGA data 135, stores the FPGA data 142 in the FPGA FMEM 141, and reconfigures the FPGA 151.
FIG. 2 is a diagram illustrating a configuration after an update of the conventional system, and a diagnosis range.
When the FPGA 151 is reconfigured by using the FPGA data 142 after an update, within the FPGA 151, the old circuits 1 to n and new circuits 191-1 and 191-2 are configured. Hereinafter, the new circuits 191-1 and 191-2 are represented as new circuits 1 and 2, respectively.
The old circuits 1 to n are the same as the old circuits 1 to n already configured before an update. However, before an update, the old circuit 1 and the old circuit 2 were connected, but after an update, the old circuit 1 and the old circuit 2 are not connected and the old circuits 1 and 2 connect with the new circuit 1.
In contrast to the FPGA 151 before an update, the new circuits 1 and 2 are added to the FPGA 151 after an update.
The new circuit 1 connects with the old circuits 1 and 2 and the new circuit 2.
The new circuit 1 is a circuit that operates at the time of normal operation of the system 101.
The new circuit 2 operates only under specific conditions and does not operate at the time of normal operation of the system 101.
It is assumed that the new circuit 1 is configured in the area including the failed portion 1 and the new circuit 2 is configured in the area including the failed portion 2. In this case, the new circuits 1 and 2 will malfunction.
In the system 101 in which the above-described update is performed, the operation of the FPGA 151 is checked by checking the whole of the system 101 for the communication behavior during normal operation.
In this case, the range of the communication behavior check includes the old circuits 1 to n and the new circuit 1 that operate by normal operation.
In other words, whether there is an error is checked by causing the old circuits 1 to n and the new circuit 1 to perform normal operation.
The new circuit 1 is a circuit that operates by normal operation of the system 101, and therefore, if there is a failed portion in the area where the new circuit 1 is configured, it is possible to detect a failure from an error in the new circuit 1. In this case, it is preferable to replace the FPGA 151 with another during the maintenance work in which the above-mentioned update etc. is performed.
On the other hand, in the operation check during normal operation, the new circuit 2 that operates only under specific conditions is not included in the range of the operation check.
Consequently, even if a failed portion is included in the new circuit 2, it is not possible to detect a failure in the new circuit 2 by the conventional operation check.
The failure in the new circuit 2 is detected in the case where the new circuit 2 operates while the system is in operation after the maintenance work has been completed. Because of this, in the case where a failed portion is included in the new circuit 2, it is needed to stop the system 101 again and to replace the FPGA 151 with another.
As above, in the operation check at the time of the conventional update, not all the circuits within the FPGA are checked and a failure in the FPGA is detected while the system is in operation after the maintenance work has been completed, and therefore, there is a problem such that reliability of the system is degraded.
If all the elements within the FPGA are diagnosed before shipment of the system, normal operation is guaranteed for any circuit configuration. However, creating such a test program will generate an enormous number of development processes and cost. Furthermore, the documents such as Japanese Laid-open Patent Publication No. 2008-52389, Japanese Laid-open Patent Publication No. 2009-44473, etc. are well known.